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My design has a clk input and a wr input. They are asynchronous so I synced the wr using the clk as follows:
always_ff @ (posedge clk)
wr_d1 <= wr;
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That is not sufficient to synchronize to clk. The register for wr_d1 has a finite probability of becoming metastable when wr violates the register setup and hold time. You need at least one more register to reduce that probability, eg.
always_ff @ (posedge clk)
begin
wr_d1 <= wr;
wr_d2 <= wr_d1;
end
Since this code would be used multiple times, you should create a sync() component.
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In another part of the code I want to use the main clock but use the write signal as a qualifier to the operation, like so:
always_ff @ (posedge clk)
begin
if (wr_d1 && (register_addr == ASMI_OPCODE)) wrote_opcode <= 1'b1;
else wrote_opcode <= 1'b0;
end
I really need the wrote_opcode signal to be asserted for only one clk cycle, so this process block needs to be triggered by the clk. So how can I set the wrote_opcode for just one clk cycle only when the wr_d1 has been asserted?
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You probably don't want to use wr_d1 (or wr_d2) in this code, what you really want is an edge-detect of when wr_d2 goes from low-to-high. You can implement that logic using another delay, eg., wr_d3 <= wr_d2, and then wr_edge <= wr_d2 and !wr_d3; (if that is the right verilog symbol for not). Then use wr_edge in your opcode logic.
Cheers,
Dave
Honored Contributor
