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Honored Contributor
Honored Contributorclock select for internal FPGA logic
HI I am working on Arria v FPGA and I am writing the code for transferring serial data to a remote module using RS-422 protocol. Here I need to dynamically change the clock rate depending on some...
Altera_ForumHonored Contributor
Honored ContributorHI Galfonz,
Thanks for the reply. I may need to write my custom transmitter and receiver as I am not following any UART protocol. The electrical characteristics of the line are just following the RS-422 specifications. Initially Tx and Rx rate will be defaluted to low baud rate and soon as I receive register configuration (from another remote module) for a higher clock rate I may need to switch to higher clock rate. So for this implemetation I would be deriving a refrence clock(125 MHz) from PLL and derive all the required clocks using clock dividers (62.5 MHz, 31.25 etc ...). I would input all these clocks to clock select core of ALTCLKCTRL and select the desired clock depending on register conf. My question would be is it possible to input the divided clocks to the ALTCLKCTRL core and can I use the clock output from core to drive my internal logic?
