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Honored Contributor
Honored Contributorclock requirement, again
I had posted this question previous but received no satisfactory answer. I have a FPGA starter training board. I have been designing some sequential circuits using the TTL macrofunctions and conventi...
Altera_ForumHonored Contributor
Honored ContributorHow fast do you want to toggle this flip-flop? What clock frequency are you trying to get out of the PLL?
The ALTPLL has a minimum output frequency - 15.625MHz for Cyclone devices with a 50MHz input clock. You don't state what frequency you're trying to get out of it but I suspect, from what you say, you're hoping for something much, much lower. To generate a clock with a much lower frequency you will have to divide it down with logic. A screen shot of your schematic might help if you're still having problems... Cheers, Alex
