Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

clock requirement, again

I had posted this question previous but received no satisfactory answer. I have a FPGA starter training board. I have been designing some sequential circuits using the TTL macrofunctions and conventi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Alex

I have received several suggestions, none of which has helped me. I do not have code, the circuit is designed using the Schematic Editor. All I want and need is how and where (other than externally) get a low-frequency clock to driver, say, a jk flip flop or a counter or any sequential circuit. Novice stuff. My initial clock is 50MHz (coming from the board clock circuits) and I take it through the ALTPLL circuit but its does not seem to work. I need someone to tell me, in simple words (or even send a circuit) on how to get this circuit. So far, I am being referred to manuals that don''t help me. The board has a clock circuit (50MHz) that is connected to Pin 10 of the ECP1C3T100C6 Cyclone.I connect this pin (via the schematic editor) to the input of the ALTPLL. A simple question: If you wanted to show how a JK FF (with J-K connected high)toggles, what kind of clock would you use?

Veronis