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Altera_Forum's avatar
Altera_Forum
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12 years ago

clock requirement, again

I had posted this question previous but received no satisfactory answer. I have a FPGA starter training board. I have been designing some sequential circuits using the TTL macrofunctions and conventi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Slacker

I read the app note you suggested. Here is what I am doing. I have all the pin numbers, and manual, etc. Chinese are not that great in their documentation. My board has a general clock circuit, which provides an output frequency of 50MHz that is connected to pin 10 of the Cyclone. I take this output and connect it to the PLL circuit. I connect the PLL output (c0) to the clock pin of the JK flip flop. I have connected the FF in toggle mode. I upload the circuit to the board and get a faint LED (not toggling). Maybe the PLL output frequency is too high for the FF.

Veronis