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Altera_Forum
Honored Contributor
Honored Contributorclock requirement, again
I had posted this question previous but received no satisfactory answer. I have a FPGA starter training board. I have been designing some sequential circuits using the TTL macrofunctions and conventi...
Altera_ForumHonored Contributor
Honored ContributorI did read the proposed application note whose link you sent me, and it was very informative. I will try the PLL approach and I assume that the input to the PLL circuit is the general clock pin from the board, which in my board is Pin 10.
Veronis
