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Altera_Forum's avatar
Altera_Forum
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18 years ago

Clock Pulse Generator

Hi, I need to generate a deterministic number of clock pulses, using PLL in Stratix device. Here is what I did: PLL --> clk0 --> counter module --> clkena1 --> clk1 I developed a coun...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hi,

Thanks for all the valuable advice. I will try to modify the design in such a way to use single clock for all the operations (to eliminate the mux).

altclkctrl only available for Stratix II device onwards.