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Honored Contributor
Honored ContributorClock Pulse Generator
Hi, I need to generate a deterministic number of clock pulses, using PLL in Stratix device. Here is what I did: PLL --> clk0 --> counter module --> clkena1 --> clk1 I developed a coun...
Altera_ForumHonored Contributor
Honored ContributorIf you can remove the clock mux, then your analysis will be much more straightforward and you should be in better shape. If it has to be there, then it has to be there, but you need to account for it. I would recommend using TimeQuest too, as it is much better clock mux analysis capabilities. Look at:
http://www.altera.com/support/examples/timequest/exm-tq-clock-mux.html
