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Altera_Forum's avatar
Altera_Forum
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19 years ago

Clock Pulse Generator

Hi, I need to generate a deterministic number of clock pulses, using PLL in Stratix device. Here is what I did: PLL --> clk0 --> counter module --> clkena1 --> clk1 I developed a coun...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

Hi,

Thanks for your input. Based on what you had said, if I am able to remove the clock mux, then I will be fine, right? Btw, the output of the clock mux is feeding other logic as well.

From Quartus report, it seems like I can achieve ~200MHz and based on the timing analysis, no hold time violation.