Clock Pulse Generator

You still have a mux on your clock, which pushes the clock edges out in time relative to the main clock, so when the PLL's output feeds logic before and after the MRAM, but not through a mux, you now have potential hold time issues. (I'm assuming this clock mux only feeds the MRAM, and not the rest of the logic around it.) Anyway, do you only use one address port per clock? If so, you can make the MRAM dual-port where one address and r/w port is based on the external clock, and the other port is based on the PLL output.