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Altera_Forum
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19 years ago

Clock Pulse Generator

Hi, I need to generate a deterministic number of clock pulses, using PLL in Stratix device. Here is what I did: PLL --> clk0 --> counter module --> clkena1 --> clk1 I developed a coun...
Altera_Forum's avatar
Altera_Forum
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19 years ago

For further discussion of why to use clock enables and the caveats when driving a clock with something like a divide-by-n register, gating logic, or muxing logic, see "Altera Forums > Device Related > FPGA Discussion > derived clock versus clock enable" at http://www.alteraforum.com/forum/showthread.php?t=754.