Clock Pulse Generator

Hi,

Exactly per what you said, the number of clock pulses is not desired, sometime it is 1 clock pulse more, sometime few cycles more. I am developing simple counter internally to count the clock pulses and observed the counter value at the output.

The clock is not going offchip. It is used internally as clock to MRAM.

Previously, I created a burst counter code to take in PLL clock and upon a signal "start", it will count number of clock pulses and gate off the output. The snippet of code is shown as below:

---------------------------------------------

// clock pulse counter

module clockBurst (

in,

out,

start,

count

);

parameter ST_IDLE=1, ST_COUNT=2, ST_DONE=3;

parameter WIDTH = 4;

input in;

output out;

input start;

input [WIDTH-1:0] count;

reg [1:0] st;

reg [1:0] ns;

reg [WIDTH-1:0] val;

wire done;

always @(negedge in)

begin

st <= ns;

end

always @(posedge in)

begin

//st <= ns;

if(ns == ST_COUNT)

val <= val + 1;

else

val <= 0;

end

always @(st or start or done)

begin

ns = st;

case (st)

ST_IDLE:

begin

if(start == 1'b0)

ns = ST_IDLE;

else

ns = ST_COUNT;

end

ST_COUNT:

begin

if(~done)

ns = ST_COUNT;

else

ns = ST_DONE;

end

ST_DONE:

begin

if(start == 1'b0)

ns = ST_IDLE;

else

ns = ST_DONE;

end

default:

begin

ns = ST_IDLE;

end

endcase

end

assign out = (st == ST_COUNT)? in : 1'b0;

assign done = (val == count)? 1'b1 : 1'b0;

endmodule

-------------------------------------

"in" is the PLL clock. "out" is the gated clock that the number of pulses rely on "count" value. I will have "start" to trigger the clock counting

Under Quartus compilation, it did show me warning message on ripple/gated clock. By using classic timing analyzer, the frequency is ~200MHz.

When I ran it, it work for PLL frequency <100MHz and start to have undeterministic clock pulse when frequency go beyond 100MHz.

Any ideas?

Thanks a lot!