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Altera_Forum
Honored Contributor
Honored ContributorClock Pulse Generator
Hi, I need to generate a deterministic number of clock pulses, using PLL in Stratix device. Here is what I did: PLL --> clk0 --> counter module --> clkena1 --> clk1 I developed a coun...
Altera_ForumHonored Contributor
Honored ContributorSounds like a Nyquest issue to me.
Why not just take double the clock Fx, pass it through a F/F that is enabled (or not) to pass the /2 clock forward. Am I missing something?
