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Honored Contributor
Honored ContributorClock Pins in Cyclone V
Hello, If I want to connect HSMA_CLK_IN_P2/N2 (which refers to CLK7p/n on my 5CSXFC6D6F31C8NES) to a PLL, I have to place the PLL in one of the two quadrants on the right of the chip, am I righ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I want to configure the PLL to be able to switch between a clock on my board ... and the received clock --- Quote End --- Are you trying to do this in a single FPGA image? Quartus is not going to let you select between two (or more) clocks to feed a single PLL. You can either: 1) Use an extenal loop - assuming you have one or can add one. Select and feed your clock out on the external loop, back into a dedicated clock pin that feeds the PLL. However, a word of warning, this will only add jitter. If you have tight jitter requirements this probably won't do. 2) Reprogram the FPGA with a different image designed to drive the same PLL from a different clock source. This is clearly dependant on your hardware supporting such a scheme. Cyclone V supports multiple images from a single boot device. If this is purely a 'lab' based project (rather than a product) then this is somewhat easier. Cheers, Alex
