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Altera_Forum
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12 years ago

Clock Pins in Cyclone V

Hello, If I want to connect HSMA_CLK_IN_P2/N2 (which refers to CLK7p/n on my 5CSXFC6D6F31C8NES) to a PLL, I have to place the PLL in one of the two quadrants on the right of the chip, am I righ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Thank you. That is exactly the text I read and, obviously, misunderstood.

Why cannot I use each clock input in conjunction with the hardware SERDES and a fractional PLL placed at X0Y74?

The fitter always complains.

Is there a way to solve this issue? For PLLs, an altclkctrl block is said to solve this, but this does not work with the serdes.