Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

clock newtork delay and intradomain skew

Hi, I have a flip flop in my fpga which is driving output pins (reg to output path). The clock of this is 5ns and the one outside fpga is 5ns (phase shifted by 90). The phase shifted clock is g...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi sstrell,

The clock for the 1st flip flop is not from PLL. It is the output clock of EMIF.

I have used the derive pll_clocks command in my .sdc file

I have attached an image for your understanding.

I will try the sdc file idea with the example you have given and let you know on the result.