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Honored Contributor
Honored Contributorclock newtork delay and intradomain skew
Hi, I have a flip flop in my fpga which is driving output pins (reg to output path). The clock of this is 5ns and the one outside fpga is 5ns (phase shifted by 90). The phase shifted clock is g...
Altera_ForumHonored Contributor
Honored ContributorHi sstrell,
The understanding by you is correct. For the flip flop within the FPGA, it is a 5ns clock and for the one outside the FPGA , it is the same 5ns but with a phase shift of 90. The following are the constraints on the output ports. I have created a virtual clock for the output delay. create_clock -name emif_clk -period 5 set_output_delay -clock emif_clk 4.5 [get_ports LC0] set_output_delay -clock emif_clk 4.5 [get_ports LC1] set_output_delay -clock emif_clk 4.5 [get_ports LC2] I have attached image of the waveform as shown in timequest GUI.
