Forum Discussion
BAro0
New Contributor
New Contributorclock multiplexing
I have a few clock signals as input and would like to internally multiplex them and generate one clock output that clocks an external device. Is it safe to use logic (LUT) muxers for a clock, knowing...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
According to the user guide, clock multiplexing can introduce glitches that create functional problems, and the delay inherent in the combinational logic can lead to timing problems. If you implement a clock multiplexer in logic cells because the design has too many clocks to use the clock control block, or if dynamic reconfiguration is too complex for your design, it is important to consider simultaneous toggling inputs and ensure glitch-free transitions. Kindly refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii51007.pdf
Figure 13–3. Glitch-Free Clock Multiplexer Structure in
Example 13–48. Verilog HDL Clock Multiplexing Design to Avoid Glitches
Thanks.
