Forum Discussion
lGuo01
New Contributor
New Contributorclock gate cell and constrains
I'm using ARRIA10 FPGA, RTL Latch based gate clock have to be used because there is no enough gate clock cells ALTCLKCTRL in this FPGA. the RTL gate cell is shown below. always @(*...
Rahul_S_Intel1
Frequent Contributor
Frequent ContributorHi,
You can mentioned it in the SDC file, normally the IO pin that is chose is recommended to dedicated clock pin
