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Altera_Forum
Honored Contributor
Honored ContributorClock failed
I got these warnings in Quartus. Please help me fix. :)
Warning: The master clock for this clock assignment could not be derived. Clock: pll|sd1|pll7|clk was not created.
Warning: Specified master clock: clk not found on or feeding the specified source node: pll|sd1|pll7|inclk
Warning: The master clock for this clock assignment could not be derived. Clock: pll|sd1|pll7|clk was not created.
Warning: Specified master clock: clk not found on or feeding the specified source node: pll|sd1|pll7|inclk
12 Replies
Altera_ForumThe PLL is connected to a Clock Source.
- Altera_Forum
It looks like your input clock to this PLL is not connected.
