Occasional Contributor
Occasional ContributorI do not understand, please give example. I have this situation with remote update (generated by Quartus megawizard) which can not run at 120 MHz, and need to lower the clock speed 8 times, still keeping the remote update clock synchronized with main design clock (passing data within same clock domain) - and looking for easiest solution, which, from my point of view, using clock enable. But remote update IP does not have clock enable input to it.
Super ContributorSo your question is a little unclear.
You're not asking specifically about clkena_test, the test code you posted. You're talking about instantiating an IP that does not include a clock enable input and you're asking how to add clock enable to something that doesn't have it. Is that correct?
If I'm interpreting this correctly, then you need to use a clock gate. But don't gate the clock directly. Use a clock control block (altclkctrl) IP, which includes an option for clock enable. Then feed the output of the clock control block to the IP that does not include clock enable.
If I'm still not interpreting this correctly, perhaps you can include a diagram or something to better explain exactly what you want/need.
Occasional Contributor
@sstrell wrote:
You're talking about instantiating an IP that does not include a clock enable input and you're asking how to add clock enable to something that doesn't have it. Is that correct?
Yes, and target design is remote update.
@sstrell wrote:
If I'm interpreting this correctly, then you need to use a clock gate. But don't gate the clock directly. Use a clock control block (altclkctrl) IP, which includes an option for clock enable. Then feed the output of the clock control block to the IP that does not include clock enable.
I am using altclkctrl in another design selecting master frequency for MP3 playback. But I am not sure if the circuit based on altclkcrtl will have output clock in the same clock domain as its input clock, and if it will appear that they are guaranteed to be synchronized, what will be final clock delay, and in which direction.
My main module, which connects remote update, uses master clock of e.g. 120 MHz. Remote update needs slower clock. Let's say these 120 MHz divided by 4 or 8 (just as an example). And I need both circuits to be fully synchronized to be able to pass multiwire data between them without metastability, ideally not using synchronizers or cross-domain handshaking (using some scarce silicon).
