Honored ContributorI have a design where I need to double an incoming frequency but lo and behold I made a mistake of not putting this input signal in a dedicated clock input pad....
so, it would appear that PLL:s can't be used now so I'm wondering if anyone has any trick how to double a frequency perhaps just with RTL or some other means. The FPGA is CIII.
Honored ContributorFor a proper fpga based design, I am afraid the notion of doubling clock without pll will get you in a timing mess.
Consider using the slow clock but use two processing channels (odd/even samples). Though a pain but should be equivalent. The problem would be at final crossover to double rate... This is equivalent to having a DDR approach inside fpga.Honored ContributorThanks. The most feasible way seems to be to add this on the list of changes for a new board spin so I can use a PLL.. I did some google search and didn't find anything either.
