Clock divider simulation problem

Hello there ,

I tried to code this clock divider to divide my input clock by 16 , but when I run simulation I got my output signal period same as my input clock , any one please can tell me why that happened ? my code

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_unsigned.all;

ENTITY TRICK IS

PORT ( CLK : IN STD_LOGIC;

F : OUT STD_LOGIC);

END TRICK;

ARCHITECTURE BEH OF TRICK IS

SIGNAL CNT : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

PROCESS (CLK) IS

BEGIN

IF (CLK'EVENT AND CLK='1') THEN

CNT<= CNT + 1;

ELSE

CNT<=CNT;

END IF;

F<=CNT(3);

END PROCESS;

END BEH;