Forum Discussion
TAdel1
New Contributor
7 years agoClock divider simulation problem
Hello there , I tried to code this clock divider to divide my input clock by 16 , but when I run simulation I got my output signal period same as my input clock , any one please can tell me why tha...
Vicky1
Regular Contributor
7 years agoHi,
what you observed in simulation result? please provide screenshot.
Have you initialized the inputs(CLK) & outputs(F,CNT) in testbench?
Regards,
Vicky