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Altera_Forum's avatar
Altera_Forum
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9 years ago

Clock data recovery

Hey, i am quite new to fpga stuff but in my current project i need to decode a 40MHz Manchester encoded signal. As far as I understood there are different ways to do this but one is to use a pll to recover the clock from the input stream.

Is this correct and if so can someone tell me how to configure the pll? (So far I only used the megafunctions to create a pll with static frequency)

I was already looking for some application notes but didn't find too much Information.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    The transceivers available in various FPGA families can be configured to perform Clock and Data Recovery (CDR) from a received serial stream. However, I suspect the data rate you're looking at may be too low. For reference look at the "Transceivers" section of the "cyclone v device handbook (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_5v3.pdf)".

    However, at 40MHz (is that 40Mbps with transitions at 80MHz?) you could consider 'simply' over-sampling the received data with a fixed local clock, possibly generated from a PLL in the manner you're familiar with.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    I would over-sample as well, unless you need to recover the clock from some reason other than decoding the data. Alex - 40Mbps Manchester = 40MHz, not 80MHz.

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Just for clarity - A 40Mbps Manchester encoded stream potentially has transitions every 12.5ns. Thus you will need to oversample what is effectively an 80Mbps signal.

    Cheers,

    Alex