Clock data recovery

The transceivers available in various FPGA families can be configured to perform Clock and Data Recovery (CDR) from a received serial stream. However, I suspect the data rate you're looking at may be too low. For reference look at the "Transceivers" section of the "cyclone v device handbook (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_5v3.pdf)".

However, at 40MHz (is that 40Mbps with transitions at 80MHz?) you could consider 'simply' over-sampling the received data with a fixed local clock, possibly generated from a PLL in the manner you're familiar with.

Cheers,

Alex