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Honored Contributor
Honored ContributorClock Constraints with PLL
A very basic question, (I am using Altium for design input but please answer as if I am using Quartus) I have a design that needs some logic that runs at 96MHz. I have an embedded processor that ...
Altera_ForumHonored Contributor
Honored ContributorWhen using a pll you should only have one input clock constrain, for your 8MHz input, with the create_clock command. Then for the two other clocks, either use the derive_pll_clocks command to create automatically, or a pair of create_generated_clock if you want to do it manually. Then you should see one line per clock in the timing report.
There is nothing wrong in using one PLL to generate both 40 MHz and 96 MHz.
