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lambert_yu's avatar
lambert_yu
Icon for Contributor rankContributor
1 year ago
Solved

Clock constrains for GPIO IP core of arria 10

Hi, all fpga : 10ax115N3f45I1sg quartus : 18.0.0 standard version Now I'm using GPIO IP core to design using bus lvds. And for this IP, I use half rate design, read and wirte use seperate cl...
Configuration
Generic Io
  • ShengN_altera's avatar
    ShengN_altera
    1 year ago

    Hi Lambert,


    Probably should be fine since there's no timing violation.

    Since that's asynchronous input and output so not need to set input delay and set output delay. Without set input delay and set output delay, you wouldn't see any timing violation one.


    Thanks,

    Regards,

    Sheng


ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi Lambert,


Probably should be fine since there's no timing violation.

Since that's asynchronous input and output so not need to set input delay and set output delay. Without set input delay and set output delay, you wouldn't see any timing violation one.


Thanks,

Regards,

Sheng