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lambert_yu's avatar
lambert_yu
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2 years ago
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Clock constrains for GPIO IP core of arria 10

Hi, all fpga : 10ax115N3f45I1sg quartus : 18.0.0 standard version Now I'm using GPIO IP core to design using bus lvds. And for this IP, I use half rate design, read and wirte use seperate cl...
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Generic Io
  • ShengN_altera's avatar
    ShengN_altera
    2 years ago

    Hi Lambert,


    Probably should be fine since there's no timing violation.

    Since that's asynchronous input and output so not need to set input delay and set output delay. Without set input delay and set output delay, you wouldn't see any timing violation one.


    Thanks,

    Regards,

    Sheng


ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi Lambert,


May I know you still got any problem with your sdc constraints?


Thanks,

Regards,

Sheng


  • lambert_yu's avatar
    lambert_yu
    Icon for Contributor rankContributor
    2 years ago

    Hi, Sheng

    Just because I designed one very simple project and there's only the instance as in the first message. And there's no timing violation. But I want to know which suitable constriants will I need to add (which I provided and related analysis is correct?) in one large project in the future. I have little confidence about this part.

    BRs,

    Lambert

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