Forum Discussion
lambert_yu
Contributor
ContributorClock constrains for GPIO IP core of arria 10
Hi, all fpga : 10ax115N3f45I1sg quartus : 18.0.0 standard version Now I'm using GPIO IP core to design using bus lvds. And for this IP, I use half rate design, read and wirte use seperate cl...
Hi Lambert,
Probably should be fine since there's no timing violation.
Since that's asynchronous input and output so not need to set input delay and set output delay. Without set input delay and set output delay, you wouldn't see any timing violation one.
Thanks,
Regards,
Sheng
ShengN_altera
Super Contributor
Super ContributorHi Lambert,
Then I think you don't need to create the virtual clock or output_clock anymore. For set_false_path, use others instead of get_clocks.
You only need to set_false_path if got any timing violation, but seems like your timing is clean then probably don't need to set_false_path as well.
