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lipingx's avatar
lipingx
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

clock configuration

FPGA: cyclone IV, EP4CE15U14A7N

external oscillator: 25MHz

My overall fpga application module will use 25MHz as system clock.

Solution 1 : use oscillator directly

Solution 2: external oscillator 25MHz ->PLL-> output 25MHz

which solution is better? why?

Configuration
  • Farabi's avatar
    Farabi
    2 years ago

    Hello,


    Advantage if using internal PLL.

    1. Using internal PLL will save cost of the board manufacturing, where you save 1 component (clock oscillator specific just for 25Mhz).
    2. You can control of your system clock skew, delay, phase using internal PLL.
    3. you can save cost again by reducing another component which is voltage regulator(if you use external oscillator, you need to supply power for the external clk osc.)


    Advantage if using external clk osc:

    1. jitter is guaranteed (but for low speed clk such as 25Mhz this is not much impact).
    2. the clock is ready when board power up. (if you using internal PLL, you need wait until FPGA enter user mode and PLL locked). If your system can't wait for this delay, you need to use external clk osc.


    regards,

    Farabi




1 Reply

  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hello,


    Advantage if using internal PLL.

    1. Using internal PLL will save cost of the board manufacturing, where you save 1 component (clock oscillator specific just for 25Mhz).
    2. You can control of your system clock skew, delay, phase using internal PLL.
    3. you can save cost again by reducing another component which is voltage regulator(if you use external oscillator, you need to supply power for the external clk osc.)


    Advantage if using external clk osc:

    1. jitter is guaranteed (but for low speed clk such as 25Mhz this is not much impact).
    2. the clock is ready when board power up. (if you using internal PLL, you need wait until FPGA enter user mode and PLL locked). If your system can't wait for this delay, you need to use external clk osc.


    regards,

    Farabi