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gyuunyuu's avatar
gyuunyuu
Icon for Contributor rankContributor
4 years ago

clkp and clkn inputs in Intel FPGAs

The clkp and clkn can be used to insert a differential clock signal into the FPGA. My question is, can we have 2 separate independent single ended clock signals being input into the FPGA on these two...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Yes, it is possible to use both P and N pins as independent single-ended clock inputs, in MAX 10 and Cyclone 10 LP devices.


Regards.


gyuunyuu's avatar
gyuunyuu
Icon for Contributor rankContributor
4 years ago

The different dedicated clock pins feed different GLCK networks. Is the fitter able to link different GCLK networks together so a single pin can feed the whole device? How does it achieve this?

Also, why does fitter allow user to use general purpose I/O pin to input a clock signal?