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Altera_Forum
Honored Contributor
Honored ContributorClassic DMA core speed?
Hi everybody, Please allow me one silly question. Let me explain small problem. I have one DMA inside Qsys, 1x 16bit PIO, SDRAM controller (16bit databus width). All peripherials are running at...
Altera_ForumHonored Contributor
Honored ContributorHi Jan:
TCM is on-chip memory, so the size will be limited. Is your SDRAM just 16 bit wide as well, or is it wider? If you are going to say a 64 bit interface, 16 bits at a time, it's going to be more efficient to pack it into 64 bit words then use the DMA to transfer the 64 bits at a time. It's something to look into at least. One thing to consider when using an different clock for the SDRAM than for the rest of your logic, this will have a latency penalty as well, since this would require clock crossing logic to prevent meta-stability. Pete
