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Altera_Forum's avatar
Altera_Forum
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13 years ago

clarification regarding writing testbench

Hello, I am writing a test bench for a ethernet packet generator module. I drive the input ports of my DUT using registers and declared the output as wire. I need some clarification on...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

By "internal registers", you mean signals with the TB, not the DUT, correct?

Probably, you'll want to use mostly always blocks -- thus, registers.