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Altera_Forum
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13 years ago

CIII: feeding ALTPLL with output of ALTCLKCTRL

Dear experts,

I'm trying to feed the output of a clock control block into a PLL and I get the following error message:

Error (15065): Clock input port inclk[0] of PLL "PLL_DOWNSTREAM:PLL_DOWNSTREAM_1|altpll:altpll_component|PLL_DOWNSTREAM_altpll:auto_generated|pll1" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block

Info (15024): Input port INCLK[0] of node "PLL_DOWNSTREAM:PLL_DOWNSTREAM_1|altpll:altpll_component|PLL_DOWNSTREAM_altpll:auto_generated|pll1" is driven by myclkctrl:CLK_SWITCH_1|myclkctrl_altclkctrl_0fi:myclkctrl_altclkctrl_0fi_component|outclk which is COMBOUT output port of Combinational cell type node myclkctrl:CLK_SWITCH_1|myclkctrl_altclkctrl_0fi:myclkctrl_altclkctrl_0fi_component|outclk

Do I need a special assignment here ?

Thanks in advance,

Michael

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Cyclone III Device Handbook, page 5-4

    " In the Cyclone III device family, dedicated clock input pins, PLL counter outputs, dual-purpose clock I/O inputs, and internal logic can all feed the clock control block for each GCLK. The output from the clock control block in turn feeds the corresponding GCLK. the gclk can drive the pll input if the clock control block inputs are outputs of another pll or dedicated clock input pins."

    I've attached a small design that shows the problem.

    Regards,

    Michael