Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

CIII: feeding ALTPLL with output of ALTCLKCTRL

Dear experts, I'm trying to feed the output of a clock control block into a PLL and I get the following error message: Error (15065): Clock input port inclk[0] of PLL "PLL_DOWNSTREAM:PLL_DOWN...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Cyclone III Device Handbook, page 5-4

" In the Cyclone III device family, dedicated clock input pins, PLL counter outputs, dual-purpose clock I/O inputs, and internal logic can all feed the clock control block for each GCLK. The output from the clock control block in turn feeds the corresponding GCLK. the gclk can drive the pll input if the clock control block inputs are outputs of another pll or dedicated clock input pins."

I've attached a small design that shows the problem.

Regards,

Michael