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Altera_Forum's avatar
Altera_Forum
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14 years ago

Chipselect in Avalon Interfaces

Hi all, I am getting used to using Quartus II and Qsys after being a long time Xilinx FPGA designer. Question or request for clarification. Altera says in the Avalon Interface Spec that ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Qsys generates a interconnection fabric which filters "read" and "write" signals from the masters accordingly to the address and the address map.

So, a slave only sees "read" and "write" signals intended for them, not for other slaves.

No clue what the chipselect signal was even intended for.