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Altera_Forum
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9 years ago

Changing the HPS SDRAM PLL clock source from QSys

Hello everyone, I'm in the early phases of design for a new board that will use a Cyclone V SE. I'm currently planning my clock domains for the HPS part and I see in several places in the Cyclo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Silly me... the question has indeed already been asked here (https://www.alteraforum.com/forum/showthread.php?t=53711)...

I found the register to modify but I don't like to manually change an automatically generated preloader before compilation... It's the best way to forget it one day. I'll file a service request.