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Altera_Forum's avatar
Altera_Forum
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9 years ago

Changing the HPS SDRAM PLL clock source from QSys

Hello everyone, I'm in the early phases of design for a new board that will use a Cyclone V SE. I'm currently planning my clock domains for the HPS part and I see in several places in the Cyclo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

It has been brought up in the forum before - I believe the Qsys setting currently does not have a straight forward (i.e. GUI) way to do that. On the other hand, the handbook does provide the register settings on the Clock Manager that seems to be able to do this - albeit in a difficult (need to modify yourself) manner