change object mode to buffer error about TFlipFlop

i see Verilog can

DT <= QQ ^ TT;

but in vhdl is not the case. How to translate Verilog above to VHDL

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY TFF3 IS

PORT (

TT, CC : IN STD_LOGIC;

QQ : OUT STD_LOGIC);

END TFF3;

ARCHITECTURE Structurala OF TFF3 IS

SIGNAL DT : STD_LOGIC;

component DFF3

PORT ( Data, Clock : IN STD_LOGIC;

DQQ : OUT STD_LOGIC);

end component;

BEGIN

DT <= QQ or TT;

Stage1:DFF3 port map (Data => DT, Clock => CC, DQQ => QQ);

END Structurala;