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FXion's avatar
FXion
Icon for New Contributor rankNew Contributor
7 years ago

Certain output signals are default high after power up

I have a customized MAX 10 board with 10M08DAF256C8G chip. One of the output signals driven by the FPGA pin P5 is high right after power up before the FPGA is programmed. After programming, the signa...
Nooraini_Y_Intel's avatar
Nooraini_Y_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi Fxion,

There is weak pull up on each MAX 10 IO pins however these IO pins are ​tri-stated when power up. The POR circuit monitors the voltage level of power supplies and keeps the I/O pins tri-stated during power up. The weak pull-up resistor in MAX 10 device I/O elements (IOE) keeps the I/O pins from floating.

Regards,

Nooraini