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vkc's avatar
vkc
Icon for New Contributor rankNew Contributor
5 years ago

CDR in automatic mode

Hii , i am using stratix 4 fpga in our design. I am using CDR in automatic mode. i followed the reset signalling according to the manual. so rx_freqlocked and pll_locked is high but rx_plllocked is ...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

HI,


It's been some time since I last heard back from you again. Hopefully you are making progress in your debug update.


Unfortunately I can't let this case idle for too long as well.


This thread will now be transitioned to community support.


If you still have follow up or new question, feel free to open a new thread to get the support from Intel support agent. Otherwise, the community users will continue to help you on this thread.


Thank you.


Regards,

dlim