Forum Discussion

vkc's avatar
vkc
Icon for New Contributor rankNew Contributor
5 years ago

CDR in automatic mode

Hii , i am using stratix 4 fpga in our design. I am using CDR in automatic mode. i followed the reset signalling according to the manual. so rx_freqlocked and pll_locked is high but rx_plllocked is ...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


I can only guide you to isolate issue but I can't help you to fix your board design or transmitter issue.


Since FPGA internal loopback design is working, you can then perform following to isolate whether it's board design or your transmitter issue

  • FPGA Tx -> board loopback via SFP loopback module -> FPGA Rx (don't use transmitter)


To isolate board design further, you can test out other Intel FPGA dev kit board if you have one


To isolate your transmitter issue, you can play around with transmitter PMA analog setting to see it helps out or check out other setting in your transmitter that may affect signal quality


Thanks.


Regards,

dlim