Forum Discussion
vkc
New Contributor
New ContributorCDR in automatic mode
Hii , i am using stratix 4 fpga in our design. I am using CDR in automatic mode. i followed the reset signalling according to the manual. so rx_freqlocked and pll_locked is high but rx_plllocked is ...
Deshi_Intel
Regular Contributor
Regular ContributorHi,
It's been a while since I last heard from you
Did you manage to isolate whether this is potential FPGA design issue or your board issue via FPGA internal loopback debug test ?
Thanks.
Regards,
dlim
vkcNew Contributor
New ContributorHiii, I tried loop back method it worked fine.I recieved the correct data BC95B5B5. I tried decreasing data rate also I still face the same issue.
I am receiving data as BC95xxxx instead of BC95B5B5 when I connect it to a transmitter .my sync_status is high. Freq_locked and rx_plllocked behaving as per the hand book. Please help.me solve this.
I am receiving data as BC95xxxx instead of BC95B5B5 when I connect it to a transmitter .my sync_status is high. Freq_locked and rx_plllocked behaving as per the hand book. Please help.me solve this.
