Forum Discussion
vkc
New Contributor
New ContributorCDR in automatic mode
Hii , i am using stratix 4 fpga in our design. I am using CDR in automatic mode. i followed the reset signalling according to the manual. so rx_freqlocked and pll_locked is high but rx_plllocked is ...
Deshi_Intel
Regular Contributor
Regular ContributorHI,
I checked the user guide doc (page 26)
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-iv/stx4_5v3.pdf
- Basically rx_pll_locked is equivalent to Rx CDR status "rx_locktorefclk" if you are using lock to ref mode else if you are using lock to data mode then you can ignore rx_pll_locked
Thanks.
Regards,
dlim
