CDR in automatic mode

Hi,

If you sync status is high, that means you already achieved synchronization and likely this is bit error issue which correlate to 8b/10b decoder status error signal rx_errdetect and rx_disperr that are toggling.

• The recommended approach to debug bit error is always to start to perform FPGA internal loopback testing to isolate whether this FPGA design issue or board design issue
• If you have debug and pointed to likely your board design issue then one quick suggestion is to reduce your data rate speed to see if it helps

The other concern I have is what's your design rx_plllocked connected to ? pll loose lock is never a good sign and you should fix this issue first else functionality failure is expected as the PLL can't generate expected clock output in stable stage.

• Are you using NativePHY or which IP that you are using ?

Thanks.

Regards,

dlim