Hii , i am using stratix 4 fpga in our design. I am using CDR in automatic mode. i followed the reset signalling according to the manual. so rx_freqlocked and pll_locked is high but rx_plllocked is ...
As the warning explained, you are not using dedicated refclk pin to provide clock to CDR causing additional jitter that's impacting the clocking network performance.
To minimize jitter impact, you should be using dedicated refclk pin from the same transceiver bank as explained in below user guide doc table 2-2 Input Reference Clock Source (page 243)
The above issue got solved. I am facing synchronization issue.I am suppose to receive BC95B5B5 sync pattern. So I gave encoded pattern of BC95 in word alignment pattern(5F115) .I am receiving BC95XXXX at the data out and sync status signal is high. I tried the byte ordering pattern with 010110101.But it didnt help.. rx_signaldetect ,pll_locked signals are high. rx_plllocked is toggling.
I can also see the rx_errdetect and rx_disperr signal toggling. Please help me solve this.
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