Forum Discussion
New ContributorCDR in automatic mode
Regular ContributorHI,
PPM setting is not related to clock frequency but rather depend on your on board crystal or clock generator chip performance.
Basically you want to relax the PPM setting by setting it to higher PPM setting like the max 1000 PPM setting if I am not mistaken.
- Then as long as your on board crystal or clock generator chip PPM performance doesn't violate the 1000PPM limit, CDR should not loose lock
Thanks.
Regards,
dlim
vkchii sir,
The issue is with refclk. my pll input clk frequency from oscillator is 100MHZ, I am using altpll ip and i am deriving two clocks 50MHZ and 62.5 MHZ. But when i see it in signal tap the 50MHZ clock which is used for calibration is correct. But 62.5MHZ clock which is given for pll_inclk and rx_cruclk is incorrect.
i am getting following warning "clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by non dedicated input".
i am using stratix 4 fpga EP4SGX530NF4513N . quartus prime 14.0 tool and i have configured pin p23 as clock. find the pll configurations file attached below. please help me solve this.
