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vkc's avatar
vkc
Icon for New Contributor rankNew Contributor
5 years ago

CDR in automatic mode

Hii , i am using stratix 4 fpga in our design. I am using CDR in automatic mode. i followed the reset signalling according to the manual. so rx_freqlocked and pll_locked is high but rx_plllocked is ...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

HI,


I have attached CDR debug checklist in earlier post.


Although the debug checklist is for Cyclone 10 GX FPGA device but the concept of CDR debug is more or less the same.


You can review the checklist to get some clue in debugging your issue. I suspect highly related to either transceiver refclk huge PPM issue or your board signal integrity issue.


Thanks.


Regards,

dlim


  • vkc's avatar
    vkc
    Icon for New Contributor rankNew Contributor
    5 years ago
    Hii, my refclk is operating at 100MHZ, what is the idle ppm to be set during configuration.