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Altera_Forum's avatar
Altera_Forum
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14 years ago

Cascading gated clock bufs in Arria 2 GX

I need (at least) two levels of gated clocks in a particular design.

For example:

Input pin drives signal called CLKIN. The CLKIN drives global or regional

clock net called CLK1A and CLK1B which are enabled with signals EN1A and

EN2A respectively.

The first clock domain is clocked from both CLK1A and CLK1B which must of

course be matched in skew.

CLK1A also drives global or regional clock nets called CLK2A and

CLK2B which are enabled with signals EN2A and EN2B respectively.

The second clock domain is clocked from both CLK1A and CLK1B which must of course be matched in skew.

I find that I cannot fit this in Arria2, since neither GCLK or RCLK can be

driven from another GCLK or RCLK.

If anyone has a solution to this I would be very grateful.

BTW - I really do want to shut down the clock with the enable, and NOT

have the enable synthesized away into logic.

:oops:

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Possible solution 1: Replace your clock gating with clock enables.

    If you can't rewrite all the code to insert clock enables, Quartus has an option to convert clock gating into clock enables. You may have to rewrite the clock gating code to match Altera's template for this.

    Possible solution 2:

    Replace your two levels of gating with a single level. Combine EN1A and EN2A to produce the gated clock CLK2A. Same for CLK2B.

    In this case, I assume you are using ALTCLKCTRL to gate the clocks. It's the only way to have low skew clock gating/muxing on Altera's FPGAs.